Capacity Determination Model with Time Constraints and Batch Processing in Semiconductor Wafer Fabrication

Recently, wafer fabrication has become more complicated and lengthened the product queue time. To ensure final product yield, engineers need to set up queue time limits for particular machines during wafer processing; we name it as “time constraints”. Time constraint problems are more serious when the time constraint is short, process is reentrant and batching. Generally, batch processing in wafer fabrication is matching these characteristics. To eradicate difficulties with time constraints and batching process, capacity planning must be addressed. This paper applied GI/G/m queuing theory to develop a capacity determination model for batch processing machines. The batching behavior is considered and taken as a factor to modify the mean and squared coefficient of variation of arrive rate in this model. By this queuing network model, the expected waiting time between machines in production systems can be estimated. Managers can also determine the capacity through the setting of expected rate of over time constraints. Furthermore, a checking table is derived for different utilizations, time constraints, and the probability of expected waiting time over time constraints. The approximate performance measures are compared with discrete-event simulation. The result shows the effectiveness of the proposed model and demonstrates that it is superior to the current planning method.